Backside thinning of image sensors is commonly used to increase their quantum efficiency and spectral range. Thinning of image sensors frequently involves bonding of the device wafers to a support wafer. See Huang et al, International Symposium on VLSI Technology and Applications, Abstract 3-3 (1989), Blouke et al, Optical Engineering, Vol. 26, No. 9,837 (1987), U.S. Pat. No. 4,266,334 to Edwards et al, issued May 12, 1981 and Hamaguchi et al, Japanese Journal of Applied Physics, Vol. 23, No. 10, L815-L817 (1984). Epoxy adhesives are used as bonding agents. A high temperature epoxy used for this application, Epotek, Epoxy Technology Inc., Billerica, MA, specifies a maximum operating temperature of 160.degree. C. This severely limits the type of thermal processing to which these epoxy bonded composites can be subjected. Specifically, post metalization sintering at 450.degree. C. is not feasible.
It has been found that imager device wafers are subjected to a net compressive stress during their fabrication which results in a typical wafer bow of 25 micrometers on a 4 inch diameter wafer. In order to effectively bond these wafers to a support wafer with a uniform bond thickness, it is necessary to bow match the device wafer to the support wafer. This requires a process to induce the correct bow on the support wafer. In practice silicon nitride layers of a specified thickness are deposited on the support wafer and then etched off one side of the support wafer to achieve a net stress. This requires extra process steps and considerable metrology as well.
Bonding of silicon wafers by contacting of hydrophillic oxidized surface layers has been studied. See Lasky, Applied Physics Letters, 48(1), (1986) and Shimbo et al, J. Applied Physics, 60(8), 1986. Recently, the technique has been developed in connection with silicon on insulator processing. See Masazara et al, J. Applied Physics, 64(10), (1988), Abe et al, Abs #291, 177th Electrochemical Society Mtg. 90-1, 460, (1990), Lehmann et al, Abs #306, 177th Electrochemical Society Mtg. 90-1, 457 (1990), Yamada et al, Abs #307, 177th Electrochemical Society Mtg., 90-1, 458 (1990) and Baumagart et al, Abs #308, 177th Electrochemical Society Mtg., 90-1, 460 (1990). U.S. Pat. No. 4,983,251 discloses that device wafers can be multiply planarized and bonded to oxide surfaces to form 3-dimensional stacked integrated circuits. This bonding method involves the joining of two silicon wafers with hydrated oxide surfaces. These surface layers must have OH-groups which create the surface attraction through hydrogen bonding during the initial wafer contact. On subsequent heating, Si--O--Si bond units form at temperatures of 300.degree. C. or higher, increasing overall bonding strength. In order to prevent voids in the bonded surfaces, the wafers must be smooth and free of particulate contamination. Surface roughness associated with integrated circuit device topography would form voids or prevent wafer bonding, even though surface OH-groups were present, because of limited surface contact area.
Wafer planarization processes have been developed to smooth device topography primarily for multilevel metal interconnections. The use of spin-on-glass (SOG) as a planarization medium is disclosed in Ito et al, J. Electrochemical Society, Vol. 137, no. 4, 1212 (1990). SOG has been used as a planarization media for device fabrication. See U.S. Pat. No. 4,968,628, Nov. 6, 1990. SOG materials are silicon containing organic compounds which are applied to wafers by spin coating. They are cured by heating, at which time they undergo a polymerization reaction in which molecules are joined with Si--O--Si bridges. There are many varieties of SOG with different organic constituents which affect their physical properties such as viscosity, hardness after curing and resistance to cracking. Generally, SOG materials called polysiloxanes have high organic content, can be coated in thicker layers and have less tendency to crack after curing. They have higher planarization capacity per coating and will therefore planarize device topography with fewer coating levels.
Planarization of oxidized silicon surfaces on a wafer scale basis has been disclosed as using a chemi-mechanical polishing process. See Rentein et al, VMIC Conference, Jun. 12-13, 1990, p. 57 (1990). U.S. Pat. No. 4,879,258 teaches that chemi-mechanical polishing can be used to planarize wafer during device fabrication. See Marks et al, VMIC Conference, Jun. 12-13, 1990, p. 89. Planarization of dielectric surfaces using boron oxide is also known. Ibid. See also U.S. Pat. No. 4,962,063. In this application boron oxide is deposited over the dielectric material and is observed to flow to effect a planarized surface. Subsequently, the boron oxide is etched away using a 1:1 dielectric to boron oxide etch.
Planarization of dielectric surfaces using the resist etchback process is similar to the boron oxide process except that the dielectric surface is planarized with photoresist. Following the planarization, the photoresist is removed with a plasma process that etches the resist and underlying dielectric at the same rate, thereby resulting in a topography which approximates the photoresist but is composed of dielectric.
This resist etchback process is reviewed by G. C. Schwartz in "Reliability of Semiconductor Devices and Interconnection and Multilevel Metallization, Interconnection, and Contact Technologies," H. Rathore, G. C. Schwartz and R. Susko, Editors, pages 310-347, The Electrochemical Society Softbound Proceedings Series, Pennington, N.J. (1989). Davari et al, IEDM Technical Digest, p. 61, 1989 reports improved planarization using in sequence a resist etchback